The present invention relates generally to variable gain amplifiers which are useful in various applications, especially as slew boost circuits for high slew rate operational amplifiers, and also in high bandwidth LDO voltage regulators that require improved transient response to instant increases (i.e. step increases) in demanded load current without use of large, external load bypass capacitors, particularly low-dropout voltage regulators (LDO voltage regulators) which are especially suited to being embedded in various integrated circuit chips that require precise internal load voltage regulation.
The closest prior art related to operational amplifiers having high slew rates is believed to include commonly owned U.S. Pat. No. 6,437,645 entitled “Slew Rate Boost Circuitry and Method” issued to Ivanov et al. on Aug. 20, 2002. A main shortcoming of this prior art is that the common-mode input voltage can not go closer than 2 gate-to-source voltages (2 VGS voltages) to the positive supply rail in a PMOS input stage.
The amount of load current demanded from a voltage regulator by some digital integrated circuits (especially by some digital integrated circuits that include digital logic circuit cells fabricated using various state-of-the-art modern integrated circuit manufacturing processes) can change instantly, i.e., within a few picoseconds, between zero and a large maximum value, e.g. 5 to 150 milliamperes while at the same time very precise power supply voltage regulation is required for the digital logic circuit cells.
Unfortunately, current consumption of some state-of-the-art digital logic circuit cells with advanced power savings features that are fabricated using state-of-the-art processes can instantly (i.e., within a few picoseconds) vary from zero to a high maximum value. Furthermore, very precise supply voltage regulation for these digital cells is required. Existing circuit topologies of LDO voltage regulators do not provide sufficiently fast transient response to supply the required load current steps, i.e., they are not capable of supplying such fast load current steps without the assistance of large load bypass capacitors. Existing topologies of LDO voltage regulator circuits do not allow sufficiently fast transient response to supply such large instantaneous increases (i.e., steps) in the amount of demanded load current without using large external load bypass capacitors that have large capacitances (in the microfarad range) connected between the output of the LDO voltage regulator and a ground supply voltage.
As a practical matter, such large load bypass capacitors can not be included in an integrated circuit chip. Although small load bypass capacitors having capacitances of up to a few nanofarads have indeed been included in digital logic circuit cells, such small load bypass capacitors are incapable of supplying large load instantaneous current steps and maintaining the precise voltage regulation needed by the digital logic circuit cells. Use of large external load bypass capacitors adds substantial cost, including the cost of the capacitors themselves, the cost of extra package pins, and the cost of the die area of the required associated bonding pads.
But most important, the large external load bypass capacitor is separated from the load by a signal bus and by its associated wirebond connection which has a parasitic inductance in 3-5 nanohenry range. The amount of voltage drop across the parasitic inductance during a large load current step exceeds the load voltage regulation requirements of the above-mentioned digital logic cells. This can make reliable operation of the digital logic cells nearly impossible.
The closest prior art related to LDO voltage regulators is believed to include the LDO voltage regulator shown in FIG. 3 of commonly owned U.S. Pat. No. 6,930,551 “Zero Voltage Class AB Minimal Delay Output Stage and Method” issued Aug. 16, 2005 to Ivanov et al. Prior Art FIG. 1 herein shows a schematic diagram of an LDO voltage regulator essentially similar to the one in FIG. 3 of the '551 patent. That LDO voltage regulator includes an input stage the output of which is connected through a source follower transistor to the output Vout. The source follower transistor has a current gain boost loop which increases its output conductance and load capacitance drive capability. The LDO voltage regulator circuitry provides large achievable small-signal bandwidth for a specified amount of current consumption and in a particular integrated circuit manufacturing process, but can not provide the fast large-signal load step response from loads the size of which range from very small load currents to very large load currents.
The present invention is related to the subject matter of the commonly assigned pending patent application, Ser. No. 12/008,533, entitled “LOW DROP VOLTAGE REGULATOR WITH INSTANT LOAD REGULATION AND METHOD”, filed by Ivanov et al. on Jan. 11, 2008, and incorporated herein by reference.
In Prior Art FIG. 1, LDO regulator 1 includes a differential input amplifier stage including differentially coupled N-channel input transistors MN1 and MN2. The gate of transistor MN1 is connected to a reference voltage Vref that can be generated by a conventional bandgap circuit. The gate of transistor MN2 is connected to a conductor 6, on which the regulated output voltage Vout of LDO voltage regulator 1 is produced by means of an output stage including P-channel pass transistor MP3 and a N-channel pull-down transistor MN4, a P-channel source follower transistor MP4, and a N-channel cascode transistor MN3. The drain of input transistor MN2 is connected by conductor 3 to the gate of source follower transistor MP4 and to a terminal of a small internal capacitor C0, which provides compensation for the feedback loop that includes input transistor MN1 and source follower transistor MP4. The source and bulk electrodes of source follower transistor MP4 are connected to output conductor 6, which also is connected to the sources of P-channel active load transistors MP1 and MP2 of the differential input stage. The drain of source follower transistor MP4 is connected by conductor 8 to the gate of pull-down transistor MN4. A constant current source 11 producing a current I1 is coupled between VSS and the source of cascode transistor MN3, the drain of which is coupled by conductor 12 to the gate of pass transistor MP3 and one terminal of a pull-up resistor R, the other terminal of which is connected to VDD. The gate of cascode transistor MN3 is connected by conductor 18 to the (+) terminal of a constant voltage source 9, the (−) terminal of which is connected to VSS. Source follower transistor MP4 is part of a current gain boost feedback loop which in effect increases the output conductance of source follower transistor MP4 and increases the load drive capability of LDO regulator 1. A load 7 is connected between Vout and VSS. One terminal of external load bypass capacitor CEXT is coupled by a wire bond to regulated output voltage conductor 6. The wire bond can be represented by its 3-5 nanohenry inductance Lwb. The other terminal of external load bypass capacitor CEXT is also connected by means of a similar wire bond inductance to the VSS conductor on the integrated circuit chip. Load 7 can be represented by a variable current source IL connected in parallel with a small internal load capacitance CINT.
The circuit structure of prior art LDO voltage regulator 1 provides a large achievable small-signal bandwidth for a chosen total current consumption and a chosen integrated circuit manufacturing process, but can not provide a suitably fast large-signal response to a step increase in the current demanded by load 7 connected to the regulated output voltage Vout on conductor 6. This is because the gate voltage of pass transistor MP3, which typically is a very large device having a gate capacitance of roughly 0.5 to 10 picofarads, may need to swing from few hundred millivolts to more than a volt in response to a step increase in the current demanded by load 7, whereas the current available to charge the gate of the pass transistor MP3 during the load current step is limited by the amount of current I1 that can be supplied by current source 11 alone.
To adequately respond to such a large instantaneous load current step, the gate voltage of pass transistor MP3 in Prior Art FIG. 1 has to swing from at least a few hundred millivolts or to as much as a volt or more. The current available to charge the large gate capacitance of pass transistor MP3 during the instantaneous load current step is limited by the value of the current I1. Consequently, for fast load response, I1 has to be chosen disproportionally large in order to provide the large slewing current demanded by the load.
Consequently, the amount of current I1 of current source 11 must be substantially increased in order to achieve a correspondingly faster response of LDO voltage regulator 1 to a step increase in the demanded load current, thereby undesirably increasing the power consumption of prior art LDO voltage regulator 1.
The LDO voltage regulator of FIG. 2, which is taken from the foregoing patent application, partially solves the foregoing problems but was found to have stability problems.
Thus, there is an unmet need for LDO voltage regulator circuitry which can provide substantially increased voltage regulator bandwidth and large slewing current without stability problems without correspondingly increased power consumption and also without stability problems.
There also is an unmet need for LDO voltage regulator circuitry which can provide a very fast, large-swing drive signal to the gate of an output transistor of the LDO voltage regulator in response to a step-current increase in the current demanded by a load to thereby provide a large slewing current without substantially increasing the quiescent current of the voltage regulator and without causing stability problems.
There also is an unmet need for an improved, more easily implementable operational amplifier having a high slew rate.